VC/H.264 and HEVC/H.265 Encoders and Decoders

The Video and Compression IP Family offers a range of hardware encoders and decoders for AVC/H.264, and HEVC/H.265 video.  

Suppor FPGA and ASIC

    Ultra high-Quality                 Ultra-low latency          
    Ultra-low power                   Ultra-small resource
    Multi channel

H.264 was developed by the ITU-T Video Coding Experts Group (VCEG) together with the ISO/IEC JTC1 Moving Picture Experts Group (MPEG). The project partnership effort is known as the Joint Video Team (JVT). The ITU-T H.264 standard and the ISO/IEC MPEG-4 AVC standard (formally, ISO/IEC 14496-10 – MPEG-4 Part 10, Advanced Video Coding) are jointly maintained so that they have identical technical content.

H.264/AVC Encoder block diagram:


H.264/AVC decoder block diagram:


High Efficiency Video Coding (HEVC) is the current joint video coding standardization project of the ITU-T Video Coding Experts Group (ITU-T Q.6/SG 16) and ISO/IEC Moving Picture Experts Group (ISO/IEC JTC 1/SC 29/WG 11).

H.265/HEVC Encoder block diagram:


H.265/HEVC Decoder block diagram:


Browse CODEC IP Cores:

1. E2X0/D2X0  Series
H.264 Baseline  I-Frame 4:2:0 8bit SD to UHD real time H.264 encoder/decoder IP Cores.

2.E5X0/D5X0  Series
H.264 Baseline  I+P Frame 4:2:0 8bit SD to UHD real time H.264 encoder/decoder IP Cores.

3.E6X0/D6X0 SeriesH.264 Mian profile I+P Frame 4:2:0 8bit SD to UHD real time H.264 encoder/decoder IP Cores.

4.E7X0/D7X0 Series
H.264 High profile I+P Frame 4:2:2/4:2:0 8bit or 4:0:0 8bit/10bit/12bit/14bit SD to UHD real time H.264 encoder/decoder IP Cores.

5.E8X0/D8X0 Series
H.264 High profile I+P Frame 4:4:4/4:2:2  8bit/10bit/12bit/14bit SD to UHD real time H.264 encoder/decoder IP Cores.

6.WDE / WiGig Codec   (WDE9X0) is E9X0/D9X0 Series
 WDE 9X0 is a set of WDE / WiGig H.264 Codec IP Core SD to UHD real time H.264 encoder/decoder IP Cores.

7.HE7X0/HD7X0 Series
HEVC/H.265  High profile I+P Frame 4:2:2/4:2:0 8bit/10bit SD to UHD real time H.264 encoder/decoder IP Cores.